1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the same and, more particularly, a semiconductor device having a capacitor and a method of manufacturing the same.
2. Description of the Prior Art
The ferroelectric capacitor of FeRAM (Ferroelectric Random Access Memory) that is mass-produced currently has the planar structure.
However, the capacitor having the stacked structure, a cell area of which can be reduced smaller, is needed in future in reply to the request for the higher integration. The stacked structure has the conductive plug, which is used to provide contact with the semiconductor substrate, directly under the lower electrode of the ferroelectric capacitor. As set forth in Patent Application Publication (KOKAI) 2001-443476, for example, it is normal that tungsten or polysilicon is used as the material of such conductive plug.
While, the FeRAM and the logic device are hybrid-integrated in many products. For example, there are the semiconductor chip used in the security field that needs the authentication, the IC card that is utilized gradually in the local self-governing body, etc.
In the logic semiconductor device, it is common that the process using the tungsten plug is employed to connect the underlying conductive pattern and the overlying conductive pattern. It is of course that, as the spice parameter used to design the circuit, the resistance value of the tungsten plug is employed.
Therefore, if the significances to make efficient use of accumulated circuit design properties and to lower the development man-hour/cost are considered, it has the great merit to use the tungsten plug as the contact plug in the logic hybrid-integrated FeRAM like the prior art.
Next, steps of forming the memory cell having the stacked capacitor will be explained hereunder.
First, steps required until a structure shown in FIG. 1A is formed will be explained hereunder.
An element isolation insulating film 102 is formed around an element forming region of a silicon substrate 101, and then a well 103 is formed in the element forming region. Then, two MOS transistors 104 are formed in one well 103.
The MOS transistors 104 have gate electrodes 104b formed on the well 103 via a gate insulating film 104a, and impurity diffusion regions 104c, 104d formed in the well 103 on both sides of the gate electrodes 104b to serve as the source/drain. Also, insulating sidewalls 105 used to form high concentration impurity regions 104e in the impurity diffusion regions 104c, 104d are formed on both side surfaces of the gate electrodes 104b. 
Then, a transistor protection insulating film 106 for covering the MOS transistors 104 is formed on the silicon substrate 101, and then a first interlayer insulating film 107 is formed on the transistor protection insulating film 106.
And, first contact holes 107a are formed in the first interlayer insulating film 107 on one impurity diffusion regions 104c of the MOS transistors 104, and then first contact plugs 108 are buried in the first contact holes 107a. 
Then, a first metal film 109, a ferroelectric film 110, and a second metal film 111 are formed sequentially on the first contact plugs 108 and the first interlayer insulating film 107. As the ferroelectric film 110, for example, a PZT film is formed.
Then, as shown in FIG. 1B, capacitors 112 are formed by patterning the first metal film 109, the ferroelectric film 110, and the second metal film 111 by virtue of the photolithography method.
In the capacitor 112, a lower electrode 109a is formed of the first metal film 109, a dielectric film 110a is formed of the ferroelectric film 110, and an upper electrode 111a is formed of the second metal film 111. The capacitor is the stacked capacitor, and the lower electrodes 109a are connected to one impurity diffusion regions 104c of the MOS transistors 104 via the underlying first contact plugs 108 respectively.
Then, as shown in FIG. 1C, a capacitor protection film 113 is formed on the capacitors 112 and the first interlayer insulating film 107. Then, a second interlayer insulating film 114 is formed on the capacitor protection film 113. Then, a second contact hole 114a is formed on the other impurity diffusion region 104d of the MOS transistors 104 by patterning the second interlayer insulating film 114, the capacitor protection film 113, the first interlayer insulating film 107, and the transistor protection insulating film 106 by virtue of the photolithography method. Then, a second contact plug 115 is formed in the second contact hole 114a. 
Next, steps required until a structure shown in FIG. 1D is formed will be explained hereunder.
Third contact holes 114b are formed on the upper electrodes 110a of the capacitors 112 by patterning the second interlayer insulating film 114 and the capacitor protection film 113. Then, a conductive film is formed on the second interlayer insulating film 114 and in the third contact holes 114b, and then this conductive film is patterned. Thus, wirings 116a connected to the upper electrodes 111a of the capacitors 112 respectively are formed and simultaneously a conductive pad 116b is formed on the second contact plug 115.
Then, a third interlayer insulating film 117 is formed on the wirings 116a, the conductive pad 116b, and the second interlayer insulating film 114. Then, a hole 117a is formed on the conductive pad 116b by patterning the third interlayer insulating film 117. Then, a fourth conductive plug 118 is formed in the hole 117a. 
Then, a bit line 118 connected to the fourth conductive plug 118 is formed on the third interlayer insulating film 117.
As the ferroelectric film 110 of the ferroelectric capacitor 112, for example, the PZT film is formed. After the formation, this PZT film is annealed in the oxygen atmosphere to crystallize. After the later etching, the recovery annealing of the PZT film, etc. are carried out in the oxygen atmosphere.
Here, the situation in which the tungsten plugs are formed as the contact plug directly under the ferroelectric capacitors shown in FIGS. 1A to 1D will be considered.
As set forth in Patent Application Publication (KOKAI) Hei 10-303398, the tungsten plug is oxidized very quickly at a low temperature. Also, oxidation of the tungsten plug spreads throughout the plug once such oxidation occurs, so that the contact failure is caused easily and reduction in the yield of the FeRAM device is brought about.
Also, even if the polysilicon is employed as the material of the contact plug, such polysilicon is also oxidized though the oxidation is not so serious as the tungsten.
By the way, as explained above, in order to improve the performance of the ferroelectric capacitor, the annealing is required in various oxygen atmospheres.
Therefore, improvement in the performance of the ferroelectric capacitor and improvement in the performance of the contact plug were in the trade-off relationship.
In contrast, various trials were made to prevent the abnormal oxidation of the tungsten plug in the crystallization annealing of the ferroelectric film or in the recovery annealing of the ferroelectric capacitor. For example, in Patent Application Publication (KOKAI) Hei 10-303398, Patent Application Publication (KOKAI) 2000-349255, Patent Application Publication (KOKAI) 2001-44377, Patent Application Publication (KOKAI) Hei 10-150155, and Patent Application Publication (KOKAI) 2000-349252, the structure in which the oxygen-barrier-metal layer is formed between the capacitor and the tungsten plug is set forth.
As described above, in the MOS transistor 104 constituting the memory cell, one impurity diffusion region 104c is connected to the ferroelectric capacitor 112 via the contact plug 108, and the other impurity diffusion region 104d is connected to the bit line 119 via another contact plug 115.
The reason why the contact plug 115 for bit-line connection is formed after the ferroelectric capacitor 112 is formed is to prevent the oxidation of the contact plug 115 in the crystallization annealing of the ferroelectric film 110 in the oxygen atmosphere or in the recovery annealing of the ferroelectric capacitor 112.
However, an aspect ratio of the contact plug 115 for bit-line connection is increased more and more with the further miniaturization in future. Therefore, technical subjects that are to be overcome newly such as the etching to form the contact hole 114a for bit-line connection, the filling of the glue layer in the contact hole 114a for bit-line connection, etc. are brought about.